HAL CORTEX constants migration ¶

This section provides information about the HAL CORTEX constants migration.

The following CORTEX constants, previously defined using #define directive , have been converted to enumerated type ( enum). This change enhances type safety and makes the code more readable and maintainable.

For more details refer to: Replace Finite Parameter Defines (Including PPP Instances) with Enum Types at HAL Levels..

HAL CORTEX NVIC priority(priority grouping/preemption/sub priority) constants ¶

HAL1	HAL2
#define NVIC_PRIORITYGROUP_0 #define NVIC_PRIORITYGROUP_1 #define NVIC_PRIORITYGROUP_2 #define NVIC_PRIORITYGROUP_3 #define NVIC_PRIORITYGROUP_4	typedef enum { HAL_CORTEX_NVIC_PRIORITY_GROUP_0, HAL_CORTEX_NVIC_PRIORITY_GROUP_1, HAL_CORTEX_NVIC_PRIORITY_GROUP_2, HAL_CORTEX_NVIC_PRIORITY_GROUP_3, HAL_CORTEX_NVIC_PRIORITY_GROUP_4 } hal_cortex_nvic_priority_group_t; /! CORTEX preemption priority enumeration definition / typedef enum { HAL_CORTEX_NVIC_PREEMP_PRIORITY_0, HAL_CORTEX_NVIC_PREEMP_PRIORITY_1, HAL_CORTEX_NVIC_PREEMP_PRIORITY_2, HAL_CORTEX_NVIC_PREEMP_PRIORITY_3, HAL_CORTEX_NVIC_PREEMP_PRIORITY_4, HAL_CORTEX_NVIC_PREEMP_PRIORITY_5, HAL_CORTEX_NVIC_PREEMP_PRIORITY_6, HAL_CORTEX_NVIC_PREEMP_PRIORITY_7, HAL_CORTEX_NVIC_PREEMP_PRIORITY_8, HAL_CORTEX_NVIC_PREEMP_PRIORITY_9, HAL_CORTEX_NVIC_PREEMP_PRIORITY_10, HAL_CORTEX_NVIC_PREEMP_PRIORITY_11, HAL_CORTEX_NVIC_PREEMP_PRIORITY_12, HAL_CORTEX_NVIC_PREEMP_PRIORITY_13, HAL_CORTEX_NVIC_PREEMP_PRIORITY_14, HAL_CORTEX_NVIC_PREEMP_PRIORITY_15 } hal_cortex_nvic_preemp_priority_t; /! CORTEX sub priority enumeration definition / typedef enum { HAL_CORTEX_NVIC_SUB_PRIORITY_0, HAL_CORTEX_NVIC_SUB_PRIORITY_1, HAL_CORTEX_NVIC_SUB_PRIORITY_2, HAL_CORTEX_NVIC_SUB_PRIORITY_3, HAL_CORTEX_NVIC_SUB_PRIORITY_4, HAL_CORTEX_NVIC_SUB_PRIORITY_5, HAL_CORTEX_NVIC_SUB_PRIORITY_6, HAL_CORTEX_NVIC_SUB_PRIORITY_7, HAL_CORTEX_NVIC_SUB_PRIORITY_8, HAL_CORTEX_NVIC_SUB_PRIORITY_9, HAL_CORTEX_NVIC_SUB_PRIORITY_10, HAL_CORTEX_NVIC_SUB_PRIORITY_11, HAL_CORTEX_NVIC_SUB_PRIORITY_12, HAL_CORTEX_NVIC_SUB_PRIORITY_13, HAL_CORTEX_NVIC_SUB_PRIORITY_14, HAL_CORTEX_NVIC_SUB_PRIORITY_15 } hal_cortex_nvic_sub_priority_t;

HAL1

HAL2

                #define NVIC_PRIORITYGROUP_0
#define NVIC_PRIORITYGROUP_1
#define NVIC_PRIORITYGROUP_2
#define NVIC_PRIORITYGROUP_3
#define NVIC_PRIORITYGROUP_4

               

                typedef enum
{
  HAL_CORTEX_NVIC_PRIORITY_GROUP_0,
  HAL_CORTEX_NVIC_PRIORITY_GROUP_1,
  HAL_CORTEX_NVIC_PRIORITY_GROUP_2,
  HAL_CORTEX_NVIC_PRIORITY_GROUP_3,
  HAL_CORTEX_NVIC_PRIORITY_GROUP_4
} hal_cortex_nvic_priority_group_t;

/*! CORTEX preemption priority enumeration definition */
typedef enum
{
  HAL_CORTEX_NVIC_PREEMP_PRIORITY_0,
  HAL_CORTEX_NVIC_PREEMP_PRIORITY_1,
  HAL_CORTEX_NVIC_PREEMP_PRIORITY_2,
  HAL_CORTEX_NVIC_PREEMP_PRIORITY_3,
  HAL_CORTEX_NVIC_PREEMP_PRIORITY_4,
  HAL_CORTEX_NVIC_PREEMP_PRIORITY_5,
  HAL_CORTEX_NVIC_PREEMP_PRIORITY_6,
  HAL_CORTEX_NVIC_PREEMP_PRIORITY_7,
  HAL_CORTEX_NVIC_PREEMP_PRIORITY_8,
  HAL_CORTEX_NVIC_PREEMP_PRIORITY_9,
  HAL_CORTEX_NVIC_PREEMP_PRIORITY_10,
  HAL_CORTEX_NVIC_PREEMP_PRIORITY_11,
  HAL_CORTEX_NVIC_PREEMP_PRIORITY_12,
  HAL_CORTEX_NVIC_PREEMP_PRIORITY_13,
  HAL_CORTEX_NVIC_PREEMP_PRIORITY_14,
  HAL_CORTEX_NVIC_PREEMP_PRIORITY_15
} hal_cortex_nvic_preemp_priority_t;

/*! CORTEX sub priority enumeration definition */
typedef enum
{
  HAL_CORTEX_NVIC_SUB_PRIORITY_0,
  HAL_CORTEX_NVIC_SUB_PRIORITY_1,
  HAL_CORTEX_NVIC_SUB_PRIORITY_2,
  HAL_CORTEX_NVIC_SUB_PRIORITY_3,
  HAL_CORTEX_NVIC_SUB_PRIORITY_4,
  HAL_CORTEX_NVIC_SUB_PRIORITY_5,
  HAL_CORTEX_NVIC_SUB_PRIORITY_6,
  HAL_CORTEX_NVIC_SUB_PRIORITY_7,
  HAL_CORTEX_NVIC_SUB_PRIORITY_8,
  HAL_CORTEX_NVIC_SUB_PRIORITY_9,
  HAL_CORTEX_NVIC_SUB_PRIORITY_10,
  HAL_CORTEX_NVIC_SUB_PRIORITY_11,
  HAL_CORTEX_NVIC_SUB_PRIORITY_12,
  HAL_CORTEX_NVIC_SUB_PRIORITY_13,
  HAL_CORTEX_NVIC_SUB_PRIORITY_14,
  HAL_CORTEX_NVIC_SUB_PRIORITY_15
} hal_cortex_nvic_sub_priority_t;

               

Key changes

Added Enumerations: The CORTEX preemption and sub-priority constants are now defined as enumerations in HAL2, whereas in HAL1 they were represented by numerical values.

HAL CORTEX SYSTICK clock source constants ¶

In HAL2, the multiple clock source defines are replaced by a simplified enum with only two options: internal or external clock source. You should map your previous clock source to one of these enum values as follows:

HAL_CORTEX_SYSTICK_CLKSOURCE_INTERNAL for clock sources like HCLK and SYSCLK.
HAL_CORTEX_SYSTICK_CLKSOURCE_EXTERNAL for clock sources such as HCLK_DIV8, LSI, LSE, SYSCLK_DIV16, and SYSCLK_DIV64.

This mapping ensures compatibility with the new HAL2 clock source configuration.

HAL1	HAL2
#define SYSTICK_CLKSOURCE_HCLK_DIV8 #define SYSTICK_CLKSOURCE_LSI #define SYSTICK_CLKSOURCE_LSE #define SYSTICK_CLKSOURCE_HCLK	typedef enum { HAL_CORTEX_SYSTICK_CLKSOURCE_INTERNAL, HAL_CORTEX_SYSTICK_CLKSOURCE_EXTERNAL } hal_cortex_systick_clk_src_t;

HAL1

HAL2

                #define SYSTICK_CLKSOURCE_HCLK_DIV8
#define SYSTICK_CLKSOURCE_LSI
#define SYSTICK_CLKSOURCE_LSE
#define SYSTICK_CLKSOURCE_HCLK

               

                typedef enum
{
  HAL_CORTEX_SYSTICK_CLKSOURCE_INTERNAL,
  HAL_CORTEX_SYSTICK_CLKSOURCE_EXTERNAL
} hal_cortex_systick_clk_src_t;

               

HAL CORTEX MPU access control constants ¶

HAL1	HAL2
#define MPU_HFNMI_PRIVDEF_NONE #define MPU_HARDFAULT_NMI #define MPU_PRIVILEGED_DEFAULT #define MPU_HFNMI_PRIVDEF	typedef enum { HAL_CORTEX_MPU_ACCESS_FAULT_ALL, HAL_CORTEX_MPU_ACCESS_FAULT_ONLY_PRIV } hal_cortex_mpu_unmapped_addr_fault_t; typedef enum { HAL_CORTEX_MPU_HARDFAULT_NMI_DISABLE, HAL_CORTEX_MPU_HARDFAULT_NMI_ENABLE } hal_cortex_mpu_hardfault_nmi_state_t;

HAL1

HAL2

                #define  MPU_HFNMI_PRIVDEF_NONE
#define  MPU_HARDFAULT_NMI

#define  MPU_PRIVILEGED_DEFAULT
#define  MPU_HFNMI_PRIVDEF

                typedef enum
{
  HAL_CORTEX_MPU_ACCESS_FAULT_ALL,
  HAL_CORTEX_MPU_ACCESS_FAULT_ONLY_PRIV
} hal_cortex_mpu_unmapped_addr_fault_t;

typedef enum
{
  HAL_CORTEX_MPU_HARDFAULT_NMI_DISABLE,
  HAL_CORTEX_MPU_HARDFAULT_NMI_ENABLE
} hal_cortex_mpu_hardfault_nmi_state_t;

               

Key changes

Split the constants: The CORTEX Access Control constants, are now split into two separate enumeration hal_cortex_mpu_unmapped_addr_fault_t and hal_cortex_mpu_hardfault_nmi_state_t.

HAL CORTEX MPU region enable constants ¶

HAL1	HAL2
#define MPU_REGION_ENABLE #define MPU_REGION_DISABLE	typedef enum { HAL_CORTEX_MPU_REGION_DISABLED, HAL_CORTEX_MPU_REGION_ENABLED } hal_cortex_mpu_region_status_t;

HAL CORTEX MPU instruction access constants ¶

HAL1	HAL2
#define MPU_INSTRUCTION_ACCESS_ENABLE #define MPU_INSTRUCTION_ACCESS_DISABLE	typedef enum { HAL_CORTEX_MPU_EXECUTION_ATTR_DISABLE, HAL_CORTEX_MPU_EXECUTION_ATTR_ENABLE } hal_cortex_mpu_execution_attr_t;

HAL1

HAL2

                #define  MPU_INSTRUCTION_ACCESS_ENABLE
#define  MPU_INSTRUCTION_ACCESS_DISABLE

                typedef enum
{
  HAL_CORTEX_MPU_EXECUTION_ATTR_DISABLE,
  HAL_CORTEX_MPU_EXECUTION_ATTR_ENABLE
} hal_cortex_mpu_execution_attr_t;

               

HAL CORTEX MPU access shareable constants ¶

HAL1	HAL2
#define MPU_ACCESS_NOT_SHAREABLE #define MPU_ACCESS_OUTER_SHAREABLE #define MPU_ACCESS_INNER_SHAREABLE	Removed in HAL2 for STM32 series with `ARMv8-M` architecture.

Important

The shareability has been removed in series with ARMv8-M but it still exist in ARMv8.1-M.

This change is related to the STM32 Hardware specifications.

HAL CORTEX MPU memory attributes constants ¶

ARM Architecture	HAL1	HAL2
`ARMv7-M` `ARMv6-M`	#define MPU_ACCESS_SHAREABLE #define MPU_ACCESS_NOT_SHAREABLE #define MPU_ACCESS_CACHEABLE #define MPU_ACCESS_NOT_CACHEABLE #define MPU_ACCESS_BUFFERABLE #define MPU_ACCESS_NOT_BUFFERABLE #define MPU_TEX_LEVEL0 #define MPU_TEX_LEVEL1 #define MPU_TEX_LEVEL2 #define MPU_TEX_LEVEL4	typedef enum { HAL_CORTEX_MPU_SO_MEM_SHAREABLE , HAL_CORTEX_MPU_DEVICE_MEM_SHAREABLE , HAL_CORTEX_MPU_NORMAL_MEM_NSHAREABLE_IO_WT_NWA , HAL_CORTEX_MPU_NORMAL_MEM_NSHAREABLE_IO_WB_NWA , HAL_CORTEX_MPU_NORMAL_MEM_SHAREABLE_IO_WT_NWA , HAL_CORTEX_MPU_NORMAL_MEM_SHAREABLE_IO_WB_NWA , HAL_CORTEX_MPU_NORMAL_MEM_NSHAREABLE_IO_NCACHEABLE , HAL_CORTEX_MPU_NORMAL_MEM_SHAREABLE_IO_NCACHEABLE , HAL_CORTEX_MPU_NORMAL_MEM_NSHAREABLE_IO_WB_RWA , HAL_CORTEX_MPU_NORMAL_MEM_SHAREABLE_IO_WB_RWA , HAL_CORTEX_MPU_DEVICE_MEM_NSHAREABLE } hal_cortex_mpu_mem_attr_t;

ARM Architecture

HAL1

HAL2

ARMv7-M

ARMv6-M

                #define  MPU_ACCESS_SHAREABLE
#define  MPU_ACCESS_NOT_SHAREABLE

#define  MPU_ACCESS_CACHEABLE
#define  MPU_ACCESS_NOT_CACHEABLE

#define  MPU_ACCESS_BUFFERABLE
#define  MPU_ACCESS_NOT_BUFFERABLE

#define  MPU_TEX_LEVEL0
#define  MPU_TEX_LEVEL1
#define  MPU_TEX_LEVEL2
#define  MPU_TEX_LEVEL4

               

                typedef enum
{
  HAL_CORTEX_MPU_SO_MEM_SHAREABLE                    ,
  HAL_CORTEX_MPU_DEVICE_MEM_SHAREABLE                ,
  HAL_CORTEX_MPU_NORMAL_MEM_NSHAREABLE_IO_WT_NWA     ,
  HAL_CORTEX_MPU_NORMAL_MEM_NSHAREABLE_IO_WB_NWA     ,
  HAL_CORTEX_MPU_NORMAL_MEM_SHAREABLE_IO_WT_NWA      ,
  HAL_CORTEX_MPU_NORMAL_MEM_SHAREABLE_IO_WB_NWA      ,
  HAL_CORTEX_MPU_NORMAL_MEM_NSHAREABLE_IO_NCACHEABLE ,
  HAL_CORTEX_MPU_NORMAL_MEM_SHAREABLE_IO_NCACHEABLE  ,
  HAL_CORTEX_MPU_NORMAL_MEM_NSHAREABLE_IO_WB_RWA     ,
  HAL_CORTEX_MPU_NORMAL_MEM_SHAREABLE_IO_WB_RWA      ,
  HAL_CORTEX_MPU_DEVICE_MEM_NSHAREABLE
} hal_cortex_mpu_mem_attr_t;

               

Important

The Shareability, Cacheablility, Bufferability and TEX levels have been replaced in series in ARMv7-M and ARMv6-M architecture with a single enumeration.

This enumeration allows the user to replace the 4 definitions used to define memory attributes in a single instruction for easier and simpler implementation.

HAL CORTEX MPU region permission attributes constants ¶

Arm Architecture	HAL1	HAL2
`ARMv8-M`	#define MPU_REGION_PRIV_RW #define MPU_REGION_ALL_RW #define MPU_REGION_PRIV_RO #define MPU_REGION_ALL_RO	typedef enum { HAL_CORTEX_MPU_REGION_ONLY_PRIV_RW, HAL_CORTEX_MPU_REGION_ALL_RW, HAL_CORTEX_MPU_REGION_ONLY_PRIV_RO, HAL_CORTEX_MPU_REGION_ALL_RO } hal_cortex_mpu_region_access_attr_t;
`ARMv7-M` `ARMv6-M`	#define MPU_REGION_NO_ACCESS #define MPU_REGION_PRIV_RW #define MPU_REGION_PRIV_RW_URO #define MPU_REGION_FULL_ACCESS #define MPU_REGION_PRIV_RO #define MPU_REGION_PRIV_RO_URO	typedef enum { HAL_CORTEX_MPU_REGION_ALL_RW_FAULT, HAL_CORTEX_MPU_REGION_ONLY_PRIV_RW, HAL_CORTEX_MPU_REGION_NPRIV_W_FAULT, HAL_CORTEX_MPU_REGION_ALL_RW, HAL_CORTEX_MPU_REGION_ONLY_PRIV_RO, HAL_CORTEX_MPU_REGION_ALL_RO } hal_cortex_mpu_region_access_attr_t;

Arm Architecture

HAL1

HAL2

ARMv8-M

                #define  MPU_REGION_PRIV_RW
#define  MPU_REGION_ALL_RW
#define  MPU_REGION_PRIV_RO
#define  MPU_REGION_ALL_RO

               

                typedef enum
{
  HAL_CORTEX_MPU_REGION_ONLY_PRIV_RW,
  HAL_CORTEX_MPU_REGION_ALL_RW,
  HAL_CORTEX_MPU_REGION_ONLY_PRIV_RO,
  HAL_CORTEX_MPU_REGION_ALL_RO
} hal_cortex_mpu_region_access_attr_t;

               

ARMv7-M

ARMv6-M

                #define  MPU_REGION_NO_ACCESS
#define  MPU_REGION_PRIV_RW
#define  MPU_REGION_PRIV_RW_URO
#define  MPU_REGION_FULL_ACCESS
#define  MPU_REGION_PRIV_RO
#define  MPU_REGION_PRIV_RO_URO

               

                typedef enum
{
  HAL_CORTEX_MPU_REGION_ALL_RW_FAULT,
  HAL_CORTEX_MPU_REGION_ONLY_PRIV_RW,
  HAL_CORTEX_MPU_REGION_NPRIV_W_FAULT,
  HAL_CORTEX_MPU_REGION_ALL_RW,
  HAL_CORTEX_MPU_REGION_ONLY_PRIV_RO,
  HAL_CORTEX_MPU_REGION_ALL_RO
} hal_cortex_mpu_region_access_attr_t;

               

HAL CORTEX MPU region number constants ¶

HAL1	HAL2
#define MPU_REGION_NUMBER0 #define MPU_REGION_NUMBER1 #define MPU_REGION_NUMBER2 #define MPU_REGION_NUMBER3 #define MPU_REGION_NUMBER4 #define MPU_REGION_NUMBER5 #define MPU_REGION_NUMBER6 #define MPU_REGION_NUMBER7 ...	typedef enum { HAL_CORTEX_MPU_REGION_0, HAL_CORTEX_MPU_REGION_1, HAL_CORTEX_MPU_REGION_2, HAL_CORTEX_MPU_REGION_3, HAL_CORTEX_MPU_REGION_4, HAL_CORTEX_MPU_REGION_5, HAL_CORTEX_MPU_REGION_6, HAL_CORTEX_MPU_REGION_7, ... } hal_cortex_mpu_region_idx_t;

HAL1

HAL2

                #define  MPU_REGION_NUMBER0
#define  MPU_REGION_NUMBER1
#define  MPU_REGION_NUMBER2
#define  MPU_REGION_NUMBER3
#define  MPU_REGION_NUMBER4
#define  MPU_REGION_NUMBER5
#define  MPU_REGION_NUMBER6
#define  MPU_REGION_NUMBER7
...

               

                typedef enum
{
  HAL_CORTEX_MPU_REGION_0,
  HAL_CORTEX_MPU_REGION_1,
  HAL_CORTEX_MPU_REGION_2,
  HAL_CORTEX_MPU_REGION_3,
  HAL_CORTEX_MPU_REGION_4,
  HAL_CORTEX_MPU_REGION_5,
  HAL_CORTEX_MPU_REGION_6,
  HAL_CORTEX_MPU_REGION_7,
  ...
} hal_cortex_mpu_region_idx_t;

               

HAL CORTEX MPU attributes number constants ¶

HAL1	HAL2
#define MPU_ATTRIBUTES_NUMBER0 #define MPU_ATTRIBUTES_NUMBER1 #define MPU_ATTRIBUTES_NUMBER2 #define MPU_ATTRIBUTES_NUMBER3 #define MPU_ATTRIBUTES_NUMBER4 #define MPU_ATTRIBUTES_NUMBER5 #define MPU_ATTRIBUTES_NUMBER6 #define MPU_ATTRIBUTES_NUMBER7	typedef enum { HAL_CORTEX_MPU_MEM_ATTR_0, HAL_CORTEX_MPU_MEM_ATTR_1, HAL_CORTEX_MPU_MEM_ATTR_2, HAL_CORTEX_MPU_MEM_ATTR_3, HAL_CORTEX_MPU_MEM_ATTR_4, HAL_CORTEX_MPU_MEM_ATTR_5, HAL_CORTEX_MPU_MEM_ATTR_6, HAL_CORTEX_MPU_MEM_ATTR_7 } hal_cortex_mpu_mem_attr_idx_t;

HAL1

HAL2

                #define  MPU_ATTRIBUTES_NUMBER0
#define  MPU_ATTRIBUTES_NUMBER1
#define  MPU_ATTRIBUTES_NUMBER2
#define  MPU_ATTRIBUTES_NUMBER3
#define  MPU_ATTRIBUTES_NUMBER4
#define  MPU_ATTRIBUTES_NUMBER5
#define  MPU_ATTRIBUTES_NUMBER6
#define  MPU_ATTRIBUTES_NUMBER7

               

                typedef enum
{
  HAL_CORTEX_MPU_MEM_ATTR_0,
  HAL_CORTEX_MPU_MEM_ATTR_1,
  HAL_CORTEX_MPU_MEM_ATTR_2,
  HAL_CORTEX_MPU_MEM_ATTR_3,
  HAL_CORTEX_MPU_MEM_ATTR_4,
  HAL_CORTEX_MPU_MEM_ATTR_5,
  HAL_CORTEX_MPU_MEM_ATTR_6,
  HAL_CORTEX_MPU_MEM_ATTR_7
} hal_cortex_mpu_mem_attr_idx_t;

               

HAL CORTEX MPU device memory attributes constants ¶

HAL1	HAL2
#define MPU_DEVICE_NGNRNE #define MPU_DEVICE_NGNRE #define MPU_DEVICE_NGRE #define MPU_DEVICE_GRE	typedef enum { HAL_CORTEX_MPU_DEVICE_MEM_NGNRNE, HAL_CORTEX_MPU_DEVICE_MEM_NGNRE, HAL_CORTEX_MPU_DEVICE_MEM_NGRE, HAL_CORTEX_MPU_DEVICE_MEM_GRE, HAL_CORTEX_MPU_DEVICE_MEM_INVALID } hal_cortex_mpu_device_mem_attr_t;

HAL1

HAL2

                #define  MPU_DEVICE_NGNRNE
#define  MPU_DEVICE_NGNRE
#define  MPU_DEVICE_NGRE
#define  MPU_DEVICE_GRE

               

                typedef enum
{
  HAL_CORTEX_MPU_DEVICE_MEM_NGNRNE,
  HAL_CORTEX_MPU_DEVICE_MEM_NGNRE,
  HAL_CORTEX_MPU_DEVICE_MEM_NGRE,
  HAL_CORTEX_MPU_DEVICE_MEM_GRE,
  HAL_CORTEX_MPU_DEVICE_MEM_INVALID
} hal_cortex_mpu_device_mem_attr_t;

               

HAL CORTEX MPU region size constants ¶

HAL1	HAL2
#define MPU_REGION_SIZE_32KB #define MPU_REGION_SIZE_64KB #define MPU_REGION_SIZE_128KB #define MPU_REGION_SIZE_256KB #define MPU_REGION_SIZE_512KB #define MPU_REGION_SIZE_1MB ...	typedef enum { HAL_CORTEX_MPU_REGION_SIZE_32KB, HAL_CORTEX_MPU_REGION_SIZE_64KB, HAL_CORTEX_MPU_REGION_SIZE_128KB, HAL_CORTEX_MPU_REGION_SIZE_256KB, HAL_CORTEX_MPU_REGION_SIZE_512KB, HAL_CORTEX_MPU_REGION_SIZE_1MB, ... } hal_cortex_mpu_device_mem_attr_t;

HAL1

HAL2

                #define   MPU_REGION_SIZE_32KB
#define   MPU_REGION_SIZE_64KB
#define   MPU_REGION_SIZE_128KB
#define   MPU_REGION_SIZE_256KB
#define   MPU_REGION_SIZE_512KB
#define   MPU_REGION_SIZE_1MB
...

               

                typedef enum
{
  HAL_CORTEX_MPU_REGION_SIZE_32KB,
  HAL_CORTEX_MPU_REGION_SIZE_64KB,
  HAL_CORTEX_MPU_REGION_SIZE_128KB,
  HAL_CORTEX_MPU_REGION_SIZE_256KB,
  HAL_CORTEX_MPU_REGION_SIZE_512KB,
  HAL_CORTEX_MPU_REGION_SIZE_1MB,
  ...
} hal_cortex_mpu_device_mem_attr_t;

               

HAL CORTEX MPU normal memory attributes constants ¶

HAL1	HAL2
#define MPU_NOT_CACHEABLE #define MPU_WRITE_THROUGH #define MPU_WRITE_BACK #define MPU_TRANSIENT #define MPU_NON_TRANSIENT #define MPU_NO_ALLOCATE #define MPU_W_ALLOCATE #define MPU_R_ALLOCATE #define MPU_RW_ALLOCATE	typedef enum { HAL_CORTEX_MPU_NORMAL_MEM_NCACHEABLE, HAL_CORTEX_MPU_NORMAL_MEM_WT_NOA, HAL_CORTEX_MPU_NORMAL_MEM_WT_WA, HAL_CORTEX_MPU_NORMAL_MEM_WT_RA, HAL_CORTEX_MPU_NORMAL_MEM_WT_RWA, HAL_CORTEX_MPU_NORMAL_MEM_WB_NOA, HAL_CORTEX_MPU_NORMAL_MEM_WB_WA, HAL_CORTEX_MPU_NORMAL_MEM_WB_RA, HAL_CORTEX_MPU_NORMAL_MEM_WB_RWA, HAL_CORTEX_MPU_NORMAL_MEM_INVALID } hal_cortex_mpu_normal_mem_cache_attr_t;

HAL1

HAL2

                #define  MPU_NOT_CACHEABLE
#define  MPU_WRITE_THROUGH
#define  MPU_WRITE_BACK
#define  MPU_TRANSIENT
#define  MPU_NON_TRANSIENT
#define  MPU_NO_ALLOCATE
#define  MPU_W_ALLOCATE
#define  MPU_R_ALLOCATE
#define  MPU_RW_ALLOCATE

               

                typedef enum
{
  HAL_CORTEX_MPU_NORMAL_MEM_NCACHEABLE,
  HAL_CORTEX_MPU_NORMAL_MEM_WT_NOA,
  HAL_CORTEX_MPU_NORMAL_MEM_WT_WA,
  HAL_CORTEX_MPU_NORMAL_MEM_WT_RA,
  HAL_CORTEX_MPU_NORMAL_MEM_WT_RWA,
  HAL_CORTEX_MPU_NORMAL_MEM_WB_NOA,
  HAL_CORTEX_MPU_NORMAL_MEM_WB_WA,
  HAL_CORTEX_MPU_NORMAL_MEM_WB_RA,
  HAL_CORTEX_MPU_NORMAL_MEM_WB_RWA,
  HAL_CORTEX_MPU_NORMAL_MEM_INVALID
} hal_cortex_mpu_normal_mem_cache_attr_t;

               

Key changes

The new enum values in hal_cortex_mpu_normal_mem_cache_attr_t combine the old defines into predefined options. This simplifies configuration, ensures compatibility, and reduces errors, making the process more intuitive for users.